When Integrated Circuits (ICs) were first introduced, they were extremely expensive and were limited in their functionality. Rapid strides in semiconductor technology have vastly reduced the cost while simultaneously increasing the performance of IC chips. However, the design, layout, and fabrication process for a dedicated, custom built IC remains quite costly. This is especially true for those instances where only a small quantity of a custom designed IC is to be manufactured. Moreover, the turn-around time (i.e., the time from initial design to a finished product) can frequently be quite lengthy, especially for complex circuit designs. For electronic and computer products, it is critical to be the first to market. Furthermore, for custom ICs, it is rather difficult to effect changes to the initial design. It takes time, effort, and money to make any necessary changes.
In view of the shortcomings associated with custom IC's, field programmable gate arrays (FPGAs) offer an attractive solution in many instances. Basically, FPGAs are standard, high-density, off-the-shelf ICs, which can be programmed by the user to a desired configuration. Circuit designers first define the desired logic functions, and the FPGA is programmed to process the input signals accordingly. Thereby, FPGA implementations can be designed, verified, and revised in a quick and efficient manner. Depending on the logic density requirements and production volumes, FPGAs are superior alternatives in terms of cost and time-to-market.
An FPGA essentially consists of an outer ring of I/O blocks surrounding an interior matrix of configurable logic blocks. The I/O blocks residing on the periphery of an FPGA are user programmable, such that each block can be programmed independently to be an input or an output and can also be tri-stated. Each logic block typically contains programmable combinatorial logic and storage registers. The combinatorial logic is used to perform Boolean functions on its input variables. Often, the registers are loaded directly from a logic block input, or they can be loaded from the combinatorial logic.
Interconnect resources occupy the channels between the rows and columns of the matrix of logic blocks and also between the logic blocks and the I/O blocks. These interconnect resources provide the flexibility to control the interconnection between two designated points on the chip. Usually, a metal network of lines runs horizontally and vertically in the rows and columns between the logic blocks. Programmable switches connect the inputs and outputs of the logic blocks and I/O blocks to these metal lines (called input & output connection boxes). Crosspoint switches and interchanges at the intersections of rows and columns are used to switch signals from one line to another (called switch boxes). Often, long lines are used to run the entire length and/or breadth of the chip.
The functions of the I/O blocks, logic blocks, and their respective interconnections are all programmable. Typically, a configuration program stored in an on-chip memory controls these functions. The configuration program is loaded automatically from an external memory upon power-up, on command, or programmed by a microprocessor as part of system initialization.
A typical symmetrical FPGA architecture is shown in the FIG. 1. FIG. 1 shows basic components and their connectivity. FIG. 1 shows a switch box and 4 connection boxes of logic block connecting to a bi-directional single length track routing fabric. The four connection boxes are identical. The Configurable logic block has its inputs connected to the routing fabric via a matrix, usually known as a connection box. Routing channels interact with each other with a matrix, known as a switch box. The switch box can be of different topologies. Recently much work has been concentrated on a superior switch box called Hyper Universal, which provides enhanced routability at the expense of some extra resources.
With further developments taking place, the connection boxes of a logic cluster shown in FIG. 1 are not in the four adjacent channels but are on all four sides of a particular switch box making the connection box and switch box appear as one single entity as shown in FIG. 2.
The disjoint switch box is very popular because of its simplicity and easy layoutability. A disjoint switch box is shown in FIG. 3. A disjoint switch box has similar one to one connection on all the sides, i.e., line number 1 of side left is connected to line number of 1 of right, top and bottom and so on. Such a switch box makes it easier for a router to predict the routability and because of of fewer number of crisscross connections it is easy to layout in silicon. However a disjoint switch box gives a reduced routability as compared to other switch boxes like Wilton, Universal & Hyper-Universal.
A typical configurable logic block would be as shown in FIG. 4. The logic block shown has a full matrix on the input side of its connectivity with the routing fabric, known as INMUX and internal feedback matrix for merged nets. It could also possibly have a full matrix on the output side to connect to the routing fabric. Generic FPGA structures are referred to in M. I. Masud. FPGA routing structures: A novel switch block and depopulated interconnect matrix architectures. Master's thesis, Department of Electrical and Computer Engineering, University of British Columbia, December 1999.
Another structure is given in G. Lemieux, P. Leventis, and D. Lewis. Generating highly-routable sparse crossbars for PLDs. In ACM/SIGDA Int. Symp. on FPGAs, pages 155-164, Monterey, Calif., February 2000.
But unlike universal switch-boxes, disjoint switch boxes are better with respect to predicting routing and are easy to layout on silicon.